FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing a design, synthesis, placement, and routing available resources on the FPGA can be the most challenging and time consuming. In order to satisfy placement and timing specifications, several iterations are often required to determine how components are to be mapped and placed on the target device and which routing resources to allocate to the components. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated mapping, placement, and routing algorithms in EDA tools perform the time consuming task of mapping, placement, and routing of components onto physical devices.
Many of the automated mapping, placement, and routing algorithms in the EDA tools are heuristic in nature. In generating a satisfactory system design, one may be required to repeat one or more of the synthesis, placement, and routing processes several times. Although the design process is automated, generating the satisfactory system design may still be time consuming, which is undesirable. For example, sub-processes such as re-synthesis, wild-card generation, and timing analysis often require a significant amount of compilation time. Although a significant investment in time is required to generate the results for these sub-processes, current EDA tools do not utilize these results in future compilations.
Thus, what is needed is an efficient and effective method and apparatus for facilitating an adaptive EDA tool that is capable of utilizing previously determined design information.